2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.std_logic_unsigned.all;
6 Port ( clk : in STD_LOGIC;
7 dac_a : out STD_LOGIC_VECTOR (4 downto 0);
8 dac_b : out STD_LOGIC_VECTOR (4 downto 0);
10 test_port : out STD_LOGIC_VECTOR (14 downto 0));
14 architecture RTL of dac is
15 signal counter : STD_LOGIC_VECTOR (20 downto 0);
17 test: process (clk) is
19 if (rising_edge(clk)) then
20 counter <= counter + '1';
22 -- 5 bit R2R DAC 0-3.3V
23 dac_a <= counter (4 downto 0);
24 dac_b <= counter (4 downto 0);
26 -- other pins without assigment
27 -- test_port <= counter (14 downto 0); -- four ports so that
29 -- test_port_d <= counter (20 downto 13); -- all pins are tested
30 -- test_pin <= counter (0); -- test single bit left over